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Reset and Reset Configuration
Table 5-3. PCI Interrupt Register Description (continued)
BI
T
4
MNEMONIC
PCI1_INTA
Function
PCI Slot 1 INTA . PCI Slot 1 Interrupt A:
PON
DEF
0
A
T
T.
R
‘0’ - no interrupt was requested
‘1’ - an interrupt was requested and waiting to be handled
5
PCI1_INTB
PCI Slot 1 INTB . PCI Slot 1 Interrupt B:
0
R
‘0’ - no interrupt was requested
‘1’ - an interrupt was requested and waiting to be handled
6
PCI1_INTC
PCI Slot 1 INTC . PCI Slot 1 Interrupt C:
0
R
‘0’ - no interrupt was requested
‘1’ - an interrupt was requested and waiting to be handled
7
PCI1_INTD
PCI Slot 1 INTD . PCI Slot 1 Interrupt D:
0
R
‘0’ - no interrupt was requested
‘1’ - an interrupt was requested and waiting to be handled
8
PCI2_INTA
PCI Slot 2 INTA . PCI Slot 2 Interrupt A:
0
R
‘0’ - no interrupt was requested
‘1’ - an interrupt was requested and waiting to be handled
9
PCI2_INTB
PCI Slot 2 INTB . PCI Slot 2 Interrupt B:
0
R
‘0’ - no interrupt was requested
‘1’ - an interrupt was requested and waiting to be handled
1
PCI2_INTC
PCI Slot 2 INTC . PCI Slot 2 Interrupt C:
0
R
0
‘0’ - no interrupt was requested
‘1’ - an interrupt was requested and waiting to be handled
11
PCI2_INTD
PCI Slot 2 INTD . PCI Slot 2 Interrupt D:
0
R
‘0’ - no interrupt was requested
‘1’ - an interrupt was requested and waiting to be handled
1
2-
Reserved
Un-implemented
R/
W
3
1
Also available is an interrupt mask register that provides the user with the option to mask
any of the possible PCI interrupt sources. It can be read or written at any time and accessed
at offset 0x4 from CS3 base address.The description of the PCI interrupt mask register is in
Table 5-4.
Chapter 5. Module Design
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